Next: Procedural Assignments, Main: Supported Constructs, Previous: Looping Statements

Continuous Assignments

A continuous assignment in Verilog is a statement that executes every time the right hand side of the an assignment changes. This is wholly equivalent to the concurrent signal assignment in VHDL with inertial delays.

Direct Sales Line: 800-804-7073 | Phone: 540-953-3390 | Email: Sales Office | Fax: 540-953-3078

Home | Timing Diagram Editor | Verilog Simulator | VHDL Verilog TestBench Generator
About SynaptiCAD

COPYRIGHT 2013, SYNAPTICAD SALES, INC., ALL RIGHTS RESERVED.