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Procedural Assignments

Procedural assignments are used to assign values to register, integers, real or time variables. These types of assignments are normally present in always/initial statements, tasks and functions. Procedural assignments can have delay, event or repeat control. All cases are translated correctly to functionally equivalent VHDL. The subtle differences when translating a Verilog procedural assignment to a VHDL assignment are handled well by Verilog2VHDL.

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