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| Next: Continuous Assignments, Main: Supported Constructs, Previous: Conditional 'casex' Looping StatementsLooping, or iteration schemes found in Verilog can be easily translated to VHDL. Verilog2VHDL supports `for', `repeat', `while' and `forever' statements. Special Note: The Verilog `for' statement is equivalent to the VHDL `for' statement only when the Verilog `for' has static bounds, and the loop variable is incremented by one or decremented by one. The loop variable is not available as a signal in VHDL, and hence cannot be accessed when used as the target for assignments, other than incrementing (decrementing) by one. For this reason, the Verilog `for' can be mapped to the VHDL `WHILE' loop . By doing so, the loop variable can also be accessed as any regular signal. |
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