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EASE Block and State Diagram HDL Entry

EASE offers the best of both worlds with your choice of graphical or text-based HDL entry. You don�t need to be a master of either Verilog or VHDL. When you're creating a new design, just enter your design using your preferred mix of graphics and text. EASE automatically generates optimized HDL code for you in the selected language - VHDL or Verilog. EASE supports industry standard version control environments that deal with design and configuration management, enabling multiple users to work simultaneously on one EASE project.

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Features & Benefits

Graphical design environment with automated generation of hierarchical VHDL or Verilog code
Push-button import of legacy Verilog or VHDL designs and extraction of graphical hierarchy
Adheres to state of the art Windows look and feel for intuitive operation
Standards compliant (IEEE-1076-87&93 VHDL and IEEE-1364 Verilog)
True multi-user design environment and associated version control, managed by a sophisticated design environment browser
Integrates smoothly with the industry's most popular simulators and synthesis tools
Platform independent database
Integrated HDL language editor
Hot error reporting

Project browser

The project browser provides a good overview and offers easy access to the design elements. The browser offers two views: the object view shows a tree of all elements in your project and the hierarchical view shows the HDL hierarchy of your project. It also provides many status details of the different objects, like verification status, 'instantiated from' info, version number and more. From the browser, all objects can be opened in their respective editor (block diagram, state diagram, truth table or text editor).

The hierarchical view shows the hierarchy on the selected entity or configuration. It allows you to create or delete configurations. Here you can also changes the binding of an architecture to a component when having multiple architectures for an entity.

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Block Diagram Editor

The block diagram editor allows you to easily decompose your system into functional blocks. It is up to you how detailed you want to make the decomposition. Each block can be implemented using one of the four available editors. Facilitating an abstraction level between block diagrams and plain HDL code, the block diagram editor allows you to graphically represent cooperating VHDL processes or Verilog always statements. The processes can be implemented using state diagrams, truth tables or HDL text. This approach visualizes the design's data flow inside a single diagram.

EASE Block Diagram Editor

State Diagram Editor

The state diagram editor supports Moore, Mealy and mixed state machines. Any valid VHDL expression or Verilog statement can be used to define actions and transition conditions. Transitions can be synchronous or asynchronous; outputs can be clocked or combinatorial. The state diagram editor supports a variety of state assignment methods, including binary, gray, one-hot and two-hot. User defined assignment is also supported. The generated HDL is optimized for time and area to achieve the best possible synthesized design from leading synthesis tools.

HDL Works State Machine Editor

Truth Table Editor

The truth table editor is useful for decoders and decision logic. The spreadsheet-like editor in combination with a flexible and smart use of column headers allows a compact visualization of the intended behavior. A column-fill wizard is available to generate data in various encoding styles and representations.

HDL Works Truth Table Editor

Integrating external HDL

External HDL files like IP, legacy code, Matlab code and FPGA generated models can be integrated in your project as external objects. EASE will create symbols and component declarations for instantiated modules. Symbols can be easily updated to the latest version of your code. Existing HDL can also be translated into block diagrams. Symbol libraries for FPGA primitives can be created on the fly from vendor VHDL or Verilog descriptions.

Verification and Linting

Before VHDL or Verilog is generated, EASE verifies the design for inconsistencies and syntax errors. Linting is an additional verification effort that identifies potential design problems (like range mismatches in assignments of vectors, or read-only signals) and optimizes the design by identifying unused signals and definitions. Errors, warnings and notes are reported in the verification pane. The messages are hot-linked to the corresponding editor to quickly navigate to the offending code.

HDLWorks Ease Lintor

Team based design

Many FPGA's and ASIC's are designed by a team of engineers that need to work closely together to finish the implementation successfully and on time. The best way to work together on a project is by using a design environment that allows a group of designers to simultaneously work on the project without interfering with each other. EASE supports team-based design using industry standard version management systems like RCS, CVS, ClearCase and Subversion. All designers in the team can check-in/check-out objects at the entity/module level. This fine grain control allows you to edit the parts that you need to work on while your colleagues can still read these parts.

3rd Party Interfacing

EASE has a user configurable third party tool flow interface. A wizard will help the user to select the appropriate tools and set the options for these tools. Extra tool buttons will be added to the GUI for easy access to the selected tools. A list of tools supported by default is provided below. Other tools or vendors are easily added through the Tcl interface.

Simulation tools:

SynaptiCAD's VeriLogger Extreme
ModelSim (Model Technology's )
NCSim, Verilog-XL (Cadence)
Silos (Silvaco)
Riviera (Aldec)
VCS (Synopsys)

Synthesis tools:

Synplify (Synplicity)
Leonardo Spectrum(Exemplar Logic)
Design Compiler family (Synopsys)

The FPGA Vendor tools from:

Actel
Altera
Xilinx

HTML Generator

The HTML Generator generator allows you to export the whole project on your intranet or to the internet. With a single click, EASE will export all diagrams, side data, generated HDL code and the project structure to the desired location in HTML and SVG files. SVG (Scalable Vector Graphics) is the W3C standard XML-based imaging model started by Adobe. Graphics created in SVG can be scaled without loss of quality across various platforms and devices. The exported HTML contains hot links in the diagrams and the project structure to easily navigate through your design.

Standards Support

EASE's code generator produces HDL output conforming to IEEE-1076-87 and IEEE-1076-93 VHDL standards, as well as the IEEE-1364 Verilog standard. EASE also supports the industry's leading simulators and synthesis tools, as well as version control features when provided.

Supported Platforms

Hardware Platforms & Operating Systems

PC
Windows 2000/XP/Vista
Linux (should work with any recent distribution). Tested with RHEL 4 and Suse 10.1
Sun SPARC
Solaris 2.7 or later

System Requirements

75 MB free disk space
256 MB system RAM (512 MB recommended)

License Configurations

Node-Locked: Windows
Floating: Windows 2000/XP/Vista, Solaris, Linux
FlexLM protected

Click here to download EASE, HDL Companion, or IO Checker

Would you like a quick walk-through of Ease? Download the evaluation version, call 800-804-7073 and ask for Gary. He will give you a brief tour which covers important areas like: block diagram editing, state machine and truth table editing.