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Module

The primary design unit in Verilog is the module. The equivalent representation in VHDL is an entity and architecture declaration. The standard Verilog and VHDL syntax for a design unit declaration are shown below:


Verilog					VHDL



module name_of_module (list_of_ports);	entity ent_name is

// input declaration				-- in port declaration

// output declaration				-- out port declaration

// inout declaration				-- inout port declaration

					end entity;



					architecture arch_name of ent_name is	

// net declaration				--  signal declaration

// register declaration				--  signal declaration

					begin

// always statement				--  process statement

endmodule				end arch_name