TestBencher Adds Support for Cycle-Based Bus Transactions

BLACKSBURG, VA, August 4, 2000 -- SynaptiCAD Inc., the design technology leader for timing diagram editing and test bench generation, today announced the release of TestBencher Pro v7.0, which provides designers with a graphical environment for generating cycle-based or time-based bus-functional models from language-independent timing diagrams. Each timing diagram created by the user is converted into an equivalent HDL transaction by the tool. Previously, only time-based transactions models could be created, but the new version allows the user to switch back and forth between time- and cycle-based representations of the transaction by specifying a clocking signal. Multiple clock domains can also be modeled in a transaction by specifying multiple clocking signals.

TestBencher Pro v7.0 also contains improved state and timing protocol checker generation for verifying the response of the model being tested. Previously, TestBencher could check the state of a signal at a given point in time using a graphical "sampling" construct. The new version enhances samples to allow sampling over a window of time and for checking for either a state change or for stability during the sampling window. Sampling window intervals can be specified as times or as clock cycles as part of the support for cycle-based test bench generation.

Another new feature is sequence recognition. With sequence recognition, users can specify in their timing diagrams a sequence of states that their system may go through and "trigger" off that sequence whenever it occurs. This feature can be used to verify that the sequence occurred, verify a set of timing requirements whenever that sequence occurs, or stimulate the design in a certain way whenever that sequence occurs. This technique is particularly useful when generating bus-functional models for "slave" devices which are designed to respond in a certain way whenever they are selected by a "bus master" device.

Overview

TestBencher Pro generates VHDL and Verilog test benches directly from timing diagrams using a bus functional approach to test bench designs. Bus-functional models execute faster than complete functional models and can be created from data contained in data sheets. A bus-functional model is also easier to maintain and debug than raw test vector data. Additionally, TestBencher's graphical representations and automatic code generation abstract coding details away from the user. This abstraction reduces the amount of time needed for test bench generation. Automating the most tedious aspects of test bench development allows engineers to focus on the design and operation of the test bench rather than the painstaking aspects of code development. The generated VHDL or Verilog code can be compiled with the model under test and simulated using all major VHDL and Verilog simulators.

Features include automatic port and signal extraction from HDL models, parameterization of both state and timing values through function call parameters or data files, checkers for signal stability and/or edge transitions within a window of time, and conditional application of edge transitions based on these checks. SynaptiCAD also offers a complete line of VHDL and Verilog model generation, simulation, and timing diagram visualization tools including: VeriLogger Pro - Verilog simulator, WaveFormer Pro - waveform translator, Timing Diagrammer Pro - timing diagram editor, and DataSheet Pro - a Data Book design tool.

Contact Information

TestBencher Pro v7.0 will be released in August 2000 on Solaris/HP-UX and Windows NT starting at $9500. For more information, contact SynaptiCAD at phone (800)804-7073 or (540)953-3390, fax (540)953-3078, email: Sales Office, web site: http://www.syncad.com. For questions concerning this press release, please contact Donna Mitchell at (540) 953-3390.