| Version 9.0 Features SynaptiCAD is proud to release version 9.0 of our product line. Version 9.0 is one of the largest updates to our software that we have ever done. Many of the features are speed improvements to the timing analysis engine, code generation engine, and signal handling routines. These make the products easier to use because most functions are now performed so quickly that you will not notice any time passage.
Multiple Timing Diagram Window option enables the user to open and edit multiple timing diagrams simultaneously. This feature is extremely useful for visually comparing different timing diagrams. View one timing diagram while drawing a similar timing diagram in the design. Also view timing diagrams and simulation results at the same time. This feature comes standard with TestBencher Pro and DataSheet Pro and is an optional feature for our other software products.
 TestBencher Pro generates test benches from graphical timing diagrams. - Multiple Timing Diagram Display included with TestBencher means that you can look at the simulation results and the transaction diagrams that were used in the simulation at the same time.
- Master and Slave Transactor control simplifies creation of bus functional models and reduces the amount of generated code.
- Added new Transaction Manager that can take lists of transactions from files, transactions applied by other interface models, and randomly generated transactions and apply them to the model under test.
- Faster TestBencher code generation. Code generation is now almost instantaneous as far as the user is concerned.
- Supports Aldec Active HDL Simulators in the External Simulator control feature. Both VHDL and Verilog versions are supported.
Interface and Bus-functional Model Generation Increased quality of test bench code generated by TestBencher. We reduced the size of the generated code by about 70%. We've also made significant enhancements in functionality of the generated code. Some new code generation features include: - Reduced number of concurrent processes generated for a diagram to simplify debugging and speed up execution of test bench
- Testbench transactions react more intuitively as expected
- Multi-bit signals can now be used as clocking signals. This, for example, allows setups and holds to be placed between two bus signals. It also allows delays and samples to be triggered relative to a multi-bit signal.
- Class Definitions and Variables can now be declared in a language independent fashion. This makes it significantly easier to reuse test benches across different verification languages. This is particularly useful for IP vendors who need to produce test benches for all verification environments used by their customers.
- Support for level-sensitive triggers from delays and samples.
- VHDL For Loops now support loop increments greater than 1 (such loops are implemented as while loops to avoid limitations of VHDL).
- Replaced timeout checks in every wait statement with a "watch-dog" timer that can abort the transaction if the timeout is exceeded.
- Added comment block to the beginning of each generated transaction file that documents settings that were used to generate the transaction.
- Able to specify the trigger order of delays and samples that are relative to a sample.
- Enhanced Verbose Output Settings to support output information about execution of samples, delays, markers, and sensitive edges.
VHDL, Verilog, and C++ Support - New C++ based library integration using the open TestBuilder libraries.
- Constrained Random Data generation with TestBuilder support.
- Temporal Equations with TestBuilder support.
- Automatic generation of TestBuilder-style test benches.
External Simulator Control
When the external program integration feature is enabled, TestBencher uses the specified programs to handle the compilation and simulation of the project. - Added support for Aldec Active-HDL and Rivera simulators.
- Automatically launches Active-HDL or ModelSim and sends commands to the graphical interface to display the test bench control and status signals.
- Automatic launching of Microsoft's C++ and GNU compiliers for SystemC and TestBuilder code.
 VeriLogger Pro is a Verilog simulator with built-in graphical test generation. - Support for PinPort devices via Verilog PLI.
- Support for SimuTAG device via Verilog PLI.
- Improved Stimulus & Results file interface.
- Ability to archive off waveform and log results from simulations runs (this also provides a handy way to make up sets of test bench stimulus diagrams for a project).
- The Stimulus and Results file allows users to specify a timing diagram to use as stimulus when Sim Diagram & Project is selected as the Simulation State. The simulation will read in stimulus from that diagram and append the simulation results waveforms to it.
- File names in the Project window are now displayed using paths relative to the project directory.
All the new WaveFormer Pro features are also in VeriLogger Pro.
 DataSheet Pro provides documentation professionals with an integrated environment for working with multiple timing diagram documents. - Multiple Timing Diagram Display included with DataSheet Pro. It makes reviewing and comparing different timing diagrams very easy.
- Improved EPS and MIF file generation
- Image views for creating multiple pictures from one timing diagram file are now easier to use and more powerful.
- OLE images update in the containing application as soon as you make a change in our timing diagram editor.
All the new WaveFormer features are also in DataSheet Pro.
 WaveFormer combines a timing diagram editor, a stimulus generator, and an interactive HDL simulator to form a rapid prototyping EDA tool that helps you design faster with fewer mistakes. Test Equipment Support - Updated Agilent Fast Binary file format reading to latest version and added support for reading signal width.
- Updated support for Agilent Logic Analyzers to support "split files" used when large waveform data sets are captured.
- Agilent Infinium Oscilloscope files can be imported into WaveFormer and used to create VHDL and Verilog test benches.
- Exponential increase in speed at which signals are collapsed into busses during VCD import.
- Added support for export data to Pulse Instruments pattern generators.
VCD and General Import Features - Import extended VCD files.
- Improved extended VCD import to handle more vendor differences.
- Speeded up VCD import when only a selected time range of VCD file is to be loaded.
- More import formats use Waveform Input dialog that supports selective signal import and auto collapsing of related signals into busses.
- Most import formats now support the use of filter files to load a selected set of signals.
- Ability to convert signals to "clock" signals.
Export and Simulation Features - Improvements to VHDL/Verilog export functionality.
- New Watch Window shows values of all signals at any time during simulation.
- Improved performance of Waveform comparison functionality (optional).
All the new Timing Diagrammer features are also in WaveFormer Pro.
 Timing Diagrammer Pro is a powerful, feature-laden timing diagram editor that lets you analyze your design in the early stages, before you have a schematic. Graphical Drawing Environment - New %F and %f dynamic text substitution codes can be used in text objects to display the timing diagram file name with and without the file extension.
- Macros can now be used in waveform segments and Boolean equations. This is a handy way to assign symbolic names to commonly used constant values such as instruction set assignments for microprocessors or constant values such as addresses on a bus.
- Improved drawing of analog signals.
- Label equations can now be specified in Perl Scripts.
- Added an example of using label equations for modeling piecewise-linear analog signals in file wfm_analog_example.pl in the SynaptiCAD/perl directory.
Timing Analysis Features - Improved signal label drawing so that more signals can fit on the screen at one time. The Track Font control keeps waveform height relative to the font size
- Speeded up drawing code for handling very large waveform files and waveform files with lots of timing parameters.
- Parameter Libraries specified with relative paths.
- Signals reordered when using a filter file to load a waveform file.
- The search function in the View Parameters in Libraries dialog now has a Find Next button, allowing users to find multiple matches for a search.
- The value entered for Clock Jitter is now distributed over the edge, instead of being doubled and applied in the positive and negative direction. This is in accordance with the TDML standard.
List of Features in Version 8.0 | 
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